Semiconductor devices or integrated circuits (ICs) can include millions of devices such as transistors. For instance, ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of devices on an IC, because of technical and market pressures, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
In a conventional integrated circuit design process, a circuit designer begins with a conceptual idea of what functions an integrated circuit is to perform. The circuit designer then creates a circuit design on a computer and verifies it using one or more simulation tools to ensure that the circuit will operate as desired. The design at this stage may be represented by what is commonly viewed as a circuit schematic, but may also be represented by higher level abstractions within the computer. These abstract designs are then converted to physical definitions of the circuit elements to be fabricated. These definitions, often called the circuit design or layout, represent the geometric boundaries for the physical devices to be fabricated—transistor gates, capacitors, resistive interconnecting wires, etc.
One limitation to achieving further reductions in the size of IC devices is conventional photolithography. In photolithography, a circuit design is transferred onto a surface or wafer by shining a light through a mask (or reticle in step-and-repeat projection systems) of the design onto a photosensitive material covering the surface. Resolution enhancement techniques (RETs), such as optical and process correction (OPC), may be used in the formation of the mask to pre-compensate for the expected optical distortions that occur in the photolithographic process. The light directed onto the mask exposes the photo-sensitive material in the pattern of the mask. A chemical process etches away either the exposed material or the unexposed material, depending on the particular process that is being used. Another chemical process etches into the wafer wherever the photosensitive material was removed. The result is the design itself, either imprinted into the wafer where the surface has been etched away, or protruding slightly from the wafer as a result of the surrounding material having been etched away.
In order to accomplish high device packing densities, smaller and smaller feature sizes are required. This includes the width and spacing of conductive features and the surface geometry, such as corners and edges of various features. Currently technologies can achieve feature sizes, i.e., critical dimensions, of 130 nm, 90 nm, and even 65 nm. It is anticipated that future design rules will require technologies that can achieve feature sizes of 45 nm and 32 nm.
Each design rule technology requires the variance in the critical dimension (CD) of that feature size to be tightly controlled. For example, in 90 nm technology an acceptable line width variance may be +/−20 nm. In determining an acceptable line width variance for smaller feature size technology, it has been customary to simply reduce the acceptable line width variance from the previous technology by a proportionate amount. For instance, in going from 90 nm technology to 65 nm technology, feature sizes have been reduced by about 30%. Accordingly the acceptable line width variance for 65 nm technology may be assumed to be reduced by about 30% of +/−20 nm, resulting in a variance of about +/−14 nm.
Variances in the CD of a feature can be attributed to inaccuracies in the mask or reticle used to produce that feature. Accordingly, as integrated circuit designs become more complicated, it becomes increasingly important that the masks used in photolithography are accurate representations of the original design layout. Unfortunately, it is unrealistic to assume that the masks can be produced without error. In the typical manufacturing process, some mask errors do occur, which may be outside the allowed variances. For instance, FIG. 1 illustrates a graph 100 plotting critical dimension (CD) values (x-axis) versus occurrences, i.e., the number of masks produced (y-axis) for a given process. A wafer fabrication company can develop a curve 101 based on a wide range of masks. Any mask having CD values between a CD lower limit 102 and a CD upper limit 103 would be considered an acceptable mask for that process.
As feature sizes continue to decrease, it becomes more and more important to ensure that the variance in the CD which can be tolerated is accurately determined. Unfortunately, simply reducing the variance from previous technologies does not ensure that the correct variance will be selected.